1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method thereof. More particularly, it relates to a nonvolatile semiconductor memory device which has a low-voltage (LV) transistor region and a high-voltage (HV) transistor region in a peripheral circuit section and which has a different element isolation structure in each of the regions.
2. Description of the Related Art
A NAND-type flash memory, for example, is a nonvolatile semiconductor memory device capable of electric rewriting (program and erase) of data. In this flash memory, a plurality of transistor circuits (peripheral circuit sections) are arranged around a memory cell section. The peripheral circuit sections of the flash memory are roughly classified into an LV transistor region and an HV transistor region.
A flash memory having such a configuration is already well known (see, for example, Jpn. Pat. Appln. KOKAI Publication No. 2002-064157).
Recently, element isolation regions have been shrinking in the NAND-type flash memory. In the future, a coating film of, for example, polysilazane (PSZ) may be used to fill a trench in the process of forming an embedded element isolation insulating film serving as shallow trench isolation (STI). That is, since the PSZ film has good coverage characteristics, it is embedded in an element isolation trench to form a micro STI.
However, the PSZ film has the property of being high in contraction stress. Thus, when the PSZ film is used for the STI of the peripheral circuit section, crystal defects tend to be happened in the LV transistor region, so that there is concern about problems such as a junction leakage. This problem is dependent on the amount of the PSZ film and can be alleviated by reducing the amount of the film, that is, by reducing the depth of the STI. However, as the STIs of the peripheral circuit sections are simultaneously formed in the LV transistor region and the HV transistor region, the reduction of the depth of the STI then leads to a problem such as an STI inversion leakage in the HV transistor region.